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/********************************************************************************************************//** |
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* @file rcc_driver.c |
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* |
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* @brief File containing the APIs for configuring the RCC peripheral. |
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* |
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* Public Functions: |
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* - uint32_t RCC_GetPCLK1Value(void) |
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* - uint32_t RCC_GetPCLK2Value(void) |
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* - uint32_t RCC_GetPLLOutputClock(void) |
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* - uint8_t RCC_SetSystemClock(RCC_Config_t RCC_Config) |
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* - uint8_t RCC_SetMCO1Clk(RCC_Config_t RCC_Config) |
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* - uint8_t RCC_SetMCO2Clk(RCC_Config_t RCC_Config) |
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* |
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* @note |
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* For further information about functions refer to the corresponding header file. |
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*/ |
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#include <stdint.h> |
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#include "stm32f446xx.h" |
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#include "rcc_driver.h" |
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/** @brief Frequency of 8 MHz */ |
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#define FREQ_8MHZ 8000000 |
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/** @brief Frequency of 16 MHz */ |
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#define FREQ_16MHZ 16000000 |
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/** @brief Possible AHB prescaler values */ |
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static uint16_t AHB_PreScaler[8] = {2, 4, 8, 16, 64, 128, 256, 512}; |
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/** @brief Possible APB prescaler values */ |
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static uint8_t APB_PreScaler[4] = {2, 4, 8, 16}; |
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/** @brief Possible PLLP prescaler values */ |
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static uint8_t PLLP_PreScaler[4] = {2, 4, 6, 8}; |
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/***********************************************************************************************************/ |
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/* Static Function Prototypes */ |
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/***********************************************************************************************************/ |
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/** |
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* @brief Function for configuring the PLL. |
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* @param[in] RCC_Config is the configuration struct. |
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* @return void. |
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*/ |
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static void RCC_PLLConfig(RCC_Config_t RCC_Config); |
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/** |
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* @brief Function for configuring the PLLI2S. |
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* @param[in] RCC_Config is the configuration struct. |
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* @return void. |
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*/ |
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static void RCC_PLLI2SConfig(RCC_Config_t RCC_Config); |
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/***********************************************************************************************************/ |
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/* Public API Definitions */ |
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/***********************************************************************************************************/ |
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uint32_t RCC_GetPCLK1Value(void){ |
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uint32_t pclk1, systemclk, clksrc; |
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uint8_t temp; |
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uint8_t ahbp, apb1p; |
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/* Check for SWS */ |
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clksrc = ((RCC->CFGR >> RCC_CFGR_SWS) & 0x3); |
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if(clksrc == 0){ |
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/* clk is HSI */ |
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systemclk = FREQ_16MHZ; |
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} |
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else if(clksrc == 1){ |
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/* clk is HSE */ |
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systemclk = FREQ_8MHZ; |
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} |
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else if(clksrc == 2){ |
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/* clk is PLL */ |
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systemclk = RCC_GetPLLOutputClock(); |
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} |
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else{ |
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/* do nothing */ |
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} |
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/* AHB prescaler */ |
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temp = ((RCC->CFGR >> RCC_CFGR_HPRE) & 0xF); |
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if(temp < 8){ |
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ahbp = 1; |
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} |
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else{ |
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ahbp = AHB_PreScaler[temp-8]; |
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} |
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/* APB1 prescaler */ |
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temp = ((RCC->CFGR >> RCC_CFGR_PPRE1) & 0x7); |
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if(temp < 4){ |
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apb1p = 1; |
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} |
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else{ |
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apb1p = APB_PreScaler[temp-4]; |
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} |
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pclk1 = (systemclk/ahbp)/apb1p; |
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return pclk1; |
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} |
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uint32_t RCC_GetPCLK2Value(void){ |
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uint32_t pclk2, systemclk, clksrc; |
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uint8_t temp; |
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uint8_t ahbp, apb2p; |
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/* Check for SWS */ |
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clksrc = ((RCC->CFGR >> RCC_CFGR_SWS) & 0x3); |
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if(clksrc == 0){ |
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/* clk is HSI */ |
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systemclk = FREQ_16MHZ; |
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} |
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else if(clksrc == 1){ |
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/* clk is HSE */ |
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systemclk = FREQ_8MHZ; |
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} |
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else if(clksrc == 2){ |
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/* clk is PLL */ |
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systemclk = RCC_GetPLLOutputClock(); |
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} |
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else{ |
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/* do nothing */ |
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} |
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/* AHB prescaler */ |
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temp = ((RCC->CFGR >> RCC_CFGR_HPRE) & 0xF); |
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if(temp < 8){ |
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ahbp = 1; |
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} |
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else{ |
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ahbp = AHB_PreScaler[temp-8]; |
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} |
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/* APB2 prescaler */ |
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temp = ((RCC->CFGR >> RCC_CFGR_PPRE2) & 0x7); |
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if(temp < 4){ |
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apb2p = 1; |
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} |
| 147 |
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else{ |
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apb2p = APB_PreScaler[temp-4]; |
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} |
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pclk2 = (systemclk/ahbp)/apb2p; |
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return pclk2; |
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} |
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uint32_t RCC_GetPLLOutputClock(void){ |
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uint8_t pllm = 0; |
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uint16_t plln = 0; |
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uint8_t pllp = 0; |
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uint32_t pll_clock = 0; |
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pllm = ((RCC->PLLCFGR >> RCC_PLLCFGR_PLLM) & 0x3F); |
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plln = ((RCC->PLLCFGR >> RCC_PLLCFGR_PLLN) & 0x01FF); |
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pllp = ((RCC->PLLCFGR >> RCC_PLLCFGR_PLLP) & 0x03); |
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if((uint8_t)(RCC->PLLCFGR >> RCC_PLLCFGR_PLLSRC) & 0x01){ |
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/* HSE oscillator clock selected as PLL clock input */ |
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pll_clock = ((uint32_t)(FREQ_8MHZ*plln)/pllm)/PLLP_PreScaler[pllp]; |
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} |
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else{ |
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/* HSI clock selected as PLL clock input */ |
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pll_clock = ((uint32_t)(FREQ_16MHZ*plln)/pllm)/PLLP_PreScaler[pllp]; |
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} |
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return pll_clock; |
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} |
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uint8_t RCC_SetSystemClock(RCC_Config_t RCC_Config){ |
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/* Check clk_source is a valid value */ |
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if(RCC_Config.clk_source > RCC_CLK_SOURCE_PLL_R){ |
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return 1; |
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} |
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| 186 |
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/* Set prescaler values */ |
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/* Clear and set AHB prescaler */ |
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RCC->CFGR &= ~(0x0F << RCC_CFGR_HPRE); |
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RCC->CFGR |= (RCC_Config.ahb_presc << RCC_CFGR_HPRE); |
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/* Clear and set APB1 prescaler */ |
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RCC->CFGR &= ~(0x07 << RCC_CFGR_PPRE1); |
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RCC->CFGR |= (RCC_Config.apb1_presc << RCC_CFGR_PPRE1); |
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/* Clear and set APB2 prescaler */ |
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RCC->CFGR &= ~(0x07 << RCC_CFGR_PPRE2); |
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RCC->CFGR |= (RCC_Config.apb2_presc << RCC_CFGR_PPRE2); |
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| 197 |
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/* Clear the RCC_CFGR_SW bits before setting */ |
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RCC->CFGR &= ~(0x03 << RCC_CFGR_SW); |
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if(RCC_Config.clk_source == RCC_CLK_SOURCE_HSI){ |
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/* Enable HSI source */ |
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RCC->CR |= (1 << RCC_CR_HSION); |
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/* Wait unitl source is ready */ |
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while(!(RCC->CR & (1 << RCC_CR_HSIRDY))); |
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/* Disable HSE source */ |
| 206 |
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RCC->CR &= ~(1 << RCC_CR_HSEON); |
| 207 |
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} |
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else if(RCC_Config.clk_source == RCC_CLK_SOURCE_HSE){ |
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/* Set HSE mode */ |
| 210 |
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if(RCC_Config.hse_mode == RCC_HSE_BYPASS){ |
| 211 |
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RCC->CR |= (1 << RCC_CR_HSEBYP); |
| 212 |
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} |
| 213 |
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else{ |
| 214 |
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RCC->CR &= ~(1 << RCC_CR_HSEBYP); |
| 215 |
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} |
| 216 |
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/* Enable HSE source */ |
| 217 |
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RCC->CR |= (1 << RCC_CR_HSEON); |
| 218 |
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/* Wait until source is ready */ |
| 219 |
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while(!(RCC->CR & (1 << RCC_CR_HSERDY))); |
| 220 |
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/* Switch to HSE source clock */ |
| 221 |
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✗ |
RCC->CFGR |= (0x01 << RCC_CFGR_SW); |
| 222 |
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/* Disable HSI source */ |
| 223 |
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RCC->CR &= ~(1 << RCC_CR_HSION); |
| 224 |
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} |
| 225 |
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else{ |
| 226 |
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/* Configure PLL */ |
| 227 |
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RCC_PLLConfig(RCC_Config); |
| 228 |
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/* Enable PLL source */ |
| 229 |
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RCC->CR |= (1 << RCC_CR_PLLON); |
| 230 |
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/* Wait until source is ready */ |
| 231 |
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while(!(RCC->CR & (1 << RCC_CR_PLLRDY))); |
| 232 |
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if(RCC_Config.clk_source == RCC_CLK_SOURCE_PLL_P){ |
| 233 |
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/* Switch to PLL source clock */ |
| 234 |
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RCC->CFGR |= (0x02 << RCC_CFGR_SW); |
| 235 |
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} |
| 236 |
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else if(RCC_Config.clk_source == RCC_CLK_SOURCE_PLL_R){ |
| 237 |
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/* Switch to PLL_R source clock */ |
| 238 |
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✗ |
RCC->CFGR |= (0x03 << RCC_CFGR_SW); |
| 239 |
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} |
| 240 |
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else{ |
| 241 |
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✗ |
return 1; |
| 242 |
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} |
| 243 |
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} |
| 244 |
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| 245 |
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return 0; |
| 246 |
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} |
| 247 |
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| 248 |
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uint8_t RCC_SetMCO1Clk(RCC_Config_t RCC_Config){ |
| 249 |
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| 250 |
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/* Check if division factor and input source are correct */ |
| 251 |
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if((RCC_Config.mco1_presc > MCO_P_5) || (RCC_Config.mco1_source > MCO1_PLL)){ |
| 252 |
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return 1; |
| 253 |
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} |
| 254 |
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| 255 |
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/* Clear and set prescaler value */ |
| 256 |
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✗ |
RCC->CFGR &= ~(0x07 << RCC_CFGR_MCO1PRE); |
| 257 |
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RCC->CFGR |= (RCC_Config.mco1_presc << RCC_CFGR_MCO1PRE); |
| 258 |
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/* Clear and set source value */ |
| 259 |
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RCC->CFGR &= ~(0x03 << RCC_CFGR_MCO1); |
| 260 |
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RCC->CFGR |= (RCC_Config.mco1_source << RCC_CFGR_MCO1); |
| 261 |
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/* Check and enable source value */ |
| 262 |
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✗ |
if(RCC_Config.mco1_source == MCO1_HSI){ |
| 263 |
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/* Enable HSI source */ |
| 264 |
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✗ |
RCC->CR |= (1 << RCC_CR_HSION); |
| 265 |
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} |
| 266 |
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✗ |
else if(RCC_Config.mco1_source == MCO1_LSE){ |
| 267 |
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/* Disalbe backup protection */ |
| 268 |
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✗ |
PWR_PCLK_EN(); |
| 269 |
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✗ |
PWR->CR |= (1 << PWR_CR_DBP); |
| 270 |
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/* Set LSE bypass */ |
| 271 |
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✗ |
if(RCC_Config.lse_bypass == RCC_LSE_BYPASS){ |
| 272 |
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✗ |
RCC->BDCR |= (1 << RCC_BDCR_LSEBYP); |
| 273 |
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} |
| 274 |
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else{ |
| 275 |
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✗ |
RCC->BDCR &= ~(1 << RCC_BDCR_LSEBYP); |
| 276 |
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} |
| 277 |
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/* Enable LSE source */ |
| 278 |
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✗ |
RCC->BDCR |= (1 << RCC_BDCR_LSEON); |
| 279 |
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} |
| 280 |
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✗ |
else if(RCC_Config.mco1_source == MCO1_HSE){ |
| 281 |
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/* Set HSE mode */ |
| 282 |
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✗ |
if(RCC_Config.hse_mode == RCC_HSE_BYPASS){ |
| 283 |
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✗ |
RCC->CR |= (1 << RCC_CR_HSEBYP); |
| 284 |
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} |
| 285 |
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else{ |
| 286 |
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✗ |
RCC->CR &= ~(1 << RCC_CR_HSEBYP); |
| 287 |
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} |
| 288 |
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/* Enable HSE source */ |
| 289 |
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✗ |
RCC->CR |= (1 << RCC_CR_HSEON); |
| 290 |
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} |
| 291 |
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else{ |
| 292 |
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/* Configure PLL */ |
| 293 |
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✗ |
RCC_PLLConfig(RCC_Config); |
| 294 |
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/* Enable PLL */ |
| 295 |
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✗ |
RCC->CR |= (1 << RCC_CR_PLLON); |
| 296 |
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} |
| 297 |
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| 298 |
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✗ |
return 0; |
| 299 |
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} |
| 300 |
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| 301 |
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✗ |
uint8_t RCC_SetMCO2Clk(RCC_Config_t RCC_Config){ |
| 302 |
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| 303 |
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/* Check if division factor is correct */ |
| 304 |
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✗ |
if(RCC_Config.mco2_presc > MCO_P_5){ |
| 305 |
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✗ |
return 1; |
| 306 |
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} |
| 307 |
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| 308 |
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/* Clear and set prescaler value */ |
| 309 |
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✗ |
RCC->CFGR &= ~(0x07 << RCC_CFGR_MCO2PRE); |
| 310 |
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✗ |
RCC->CFGR |= (RCC_Config.mco2_presc << RCC_CFGR_MCO2PRE); |
| 311 |
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/* Clear and set source value */ |
| 312 |
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✗ |
RCC->CFGR &= ~(0x03 << RCC_CFGR_MCO2); |
| 313 |
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✗ |
RCC->CFGR |= (RCC_Config.mco2_source << RCC_CFGR_MCO2); |
| 314 |
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/* Check and enable source value */ |
| 315 |
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✗ |
if(RCC_Config.mco2_source == MCO2_SYSCLK){ |
| 316 |
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/* Do nothing */ |
| 317 |
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} |
| 318 |
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✗ |
else if(RCC_Config.mco2_source == MCO2_PLLI2S){ |
| 319 |
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/* Configure PLLI2S */ |
| 320 |
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✗ |
RCC_PLLI2SConfig(RCC_Config); |
| 321 |
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/* Enable PLLI2S */ |
| 322 |
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✗ |
RCC->CR |= (1 << RCC_CR_PLLI2SON); |
| 323 |
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} |
| 324 |
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✗ |
else if(RCC_Config.mco2_source == MCO2_HSE){ |
| 325 |
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/* Set HSE mode */ |
| 326 |
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✗ |
if(RCC_Config.hse_mode == RCC_HSE_BYPASS){ |
| 327 |
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✗ |
RCC->CR |= (1 << RCC_CR_HSEBYP); |
| 328 |
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} |
| 329 |
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else{ |
| 330 |
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✗ |
RCC->CR &= ~(1 << RCC_CR_HSEBYP); |
| 331 |
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} |
| 332 |
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/* Enable HSE source */ |
| 333 |
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✗ |
RCC->CR |= (1 << RCC_CR_HSEON); |
| 334 |
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} |
| 335 |
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else{ |
| 336 |
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/* Configure PLL */ |
| 337 |
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✗ |
RCC_PLLConfig(RCC_Config); |
| 338 |
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/* Enable PLL */ |
| 339 |
|
✗ |
RCC->CR |= (1 << RCC_CR_PLLON); |
| 340 |
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} |
| 341 |
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| 342 |
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✗ |
return 0; |
| 343 |
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} |
| 344 |
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| 345 |
|
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/***********************************************************************************************************/ |
| 346 |
|
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/* Static Function Definitions */ |
| 347 |
|
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/***********************************************************************************************************/ |
| 348 |
|
|
|
| 349 |
|
✗ |
static void RCC_PLLConfig(RCC_Config_t RCC_Config){ |
| 350 |
|
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|
| 351 |
|
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/* Clear and set R prescaler division factor */ |
| 352 |
|
✗ |
RCC->PLLCFGR &= ~(0x07 << RCC_PLLCFGR_PLLR); |
| 353 |
|
✗ |
RCC->PLLCFGR |= (RCC_Config.pll_r << RCC_PLLCFGR_PLLR); |
| 354 |
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|
/* Clear and set Q prescaler division factor */ |
| 355 |
|
✗ |
RCC->PLLCFGR &= ~(0x0F << RCC_PLLCFGR_PLLQ); |
| 356 |
|
✗ |
RCC->PLLCFGR |= (RCC_Config.pll_q << RCC_PLLCFGR_PLLQ); |
| 357 |
|
|
/* Clear and set P prescaler division factor */ |
| 358 |
|
✗ |
RCC->PLLCFGR &= ~(0x03 << RCC_PLLCFGR_PLLP); |
| 359 |
|
✗ |
RCC->PLLCFGR |= (RCC_Config.pll_p << RCC_PLLCFGR_PLLP); |
| 360 |
|
|
/* Clear and set N prescaler multiplication value */ |
| 361 |
|
✗ |
RCC->PLLCFGR &= ~(0x01FF << RCC_PLLCFGR_PLLN); |
| 362 |
|
✗ |
RCC->PLLCFGR |= (RCC_Config.pll_n << RCC_PLLCFGR_PLLN); |
| 363 |
|
|
/* Clear and set M prescaler division factor */ |
| 364 |
|
✗ |
RCC->PLLCFGR &= ~(0x3F << RCC_PLLCFGR_PLLM); |
| 365 |
|
✗ |
RCC->PLLCFGR |= (RCC_Config.pll_m << RCC_PLLCFGR_PLLM); |
| 366 |
|
|
/* Clear and set input source for PLL */ |
| 367 |
|
✗ |
RCC->PLLCFGR &= ~(0x01 << RCC_PLLCFGR_PLLSRC); |
| 368 |
|
✗ |
RCC->PLLCFGR |= (RCC_Config.pll_source << RCC_PLLCFGR_PLLSRC); |
| 369 |
|
|
|
| 370 |
|
|
/* Enable input source for PLL */ |
| 371 |
|
✗ |
if(RCC_Config.pll_source == PLL_SOURCE_HSI){ |
| 372 |
|
|
/* Enable HSI source */ |
| 373 |
|
✗ |
RCC->CR |= (1 << RCC_CR_HSION); |
| 374 |
|
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} |
| 375 |
|
✗ |
else if(RCC_Config.pll_source == PLL_SOURCE_HSE){ |
| 376 |
|
|
/* Set HSE mode */ |
| 377 |
|
✗ |
if(RCC_Config.hse_mode == RCC_HSE_BYPASS){ |
| 378 |
|
✗ |
RCC->CR |= (1 << RCC_CR_HSEBYP); |
| 379 |
|
|
} |
| 380 |
|
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else{ |
| 381 |
|
✗ |
RCC->CR &= ~(1 << RCC_CR_HSEBYP); |
| 382 |
|
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} |
| 383 |
|
|
/* Enable HSE source */ |
| 384 |
|
✗ |
RCC->CR |= (1 << RCC_CR_HSEON); |
| 385 |
|
|
} |
| 386 |
|
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else{ |
| 387 |
|
|
/* do nothing */ |
| 388 |
|
|
} |
| 389 |
|
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} |
| 390 |
|
|
|
| 391 |
|
✗ |
static void RCC_PLLI2SConfig(RCC_Config_t RCC_Config){ |
| 392 |
|
|
|
| 393 |
|
|
/* Clear and set R prescaler division factor */ |
| 394 |
|
✗ |
RCC->PLLI2SCFGR &= ~(0x07 << RCC_PLLI2SCFGR_PLLI2SR); |
| 395 |
|
✗ |
RCC->PLLI2SCFGR |= (RCC_Config.plli2s_r << RCC_PLLI2SCFGR_PLLI2SR); |
| 396 |
|
|
/* Clear and set Q prescaler division factor */ |
| 397 |
|
✗ |
RCC->PLLI2SCFGR &= ~(0x0F << RCC_PLLI2SCFGR_PLLI2SQ); |
| 398 |
|
✗ |
RCC->PLLI2SCFGR |= (RCC_Config.plli2s_q << RCC_PLLI2SCFGR_PLLI2SQ); |
| 399 |
|
|
/* Clear and set P prescaler division factor */ |
| 400 |
|
✗ |
RCC->PLLI2SCFGR &= ~(0x03 << RCC_PLLI2SCFGR_PLLI2SP); |
| 401 |
|
✗ |
RCC->PLLI2SCFGR |= (RCC_Config.plli2s_p << RCC_PLLI2SCFGR_PLLI2SP); |
| 402 |
|
|
/* Clear and set N prescaler multiplication value */ |
| 403 |
|
✗ |
RCC->PLLI2SCFGR &= ~(0x01FF << RCC_PLLI2SCFGR_PLLI2SN); |
| 404 |
|
✗ |
RCC->PLLI2SCFGR |= (RCC_Config.plli2s_n << RCC_PLLI2SCFGR_PLLI2SN); |
| 405 |
|
|
/* Clear and set M prescaler division factor */ |
| 406 |
|
✗ |
RCC->PLLI2SCFGR &= ~(0x3F << RCC_PLLI2SCFGR_PLLI2SM); |
| 407 |
|
✗ |
RCC->PLLI2SCFGR |= (RCC_Config.plli2s_m << RCC_PLLI2SCFGR_PLLI2SM); |
| 408 |
|
|
/* Clear and set input source for PLLI2S */ |
| 409 |
|
✗ |
RCC->PLLCFGR &= ~(0x01 << RCC_PLLCFGR_PLLSRC); |
| 410 |
|
✗ |
RCC->PLLCFGR |= (RCC_Config.pll_source << RCC_PLLCFGR_PLLSRC); |
| 411 |
|
|
|
| 412 |
|
|
/* Enable input source for PLLI2S */ |
| 413 |
|
✗ |
if(RCC_Config.pll_source == PLL_SOURCE_HSI){ |
| 414 |
|
|
/* Enable HSI source */ |
| 415 |
|
✗ |
RCC->CR |= (1 << RCC_CR_HSION); |
| 416 |
|
|
} |
| 417 |
|
✗ |
else if(RCC_Config.pll_source == PLL_SOURCE_HSE){ |
| 418 |
|
|
/* Set HSE mode */ |
| 419 |
|
✗ |
if(RCC_Config.hse_mode == RCC_HSE_BYPASS){ |
| 420 |
|
✗ |
RCC->CR |= (1 << RCC_CR_HSEBYP); |
| 421 |
|
|
} |
| 422 |
|
|
else{ |
| 423 |
|
✗ |
RCC->CR &= ~(1 << RCC_CR_HSEBYP); |
| 424 |
|
|
} |
| 425 |
|
|
/* Enable HSE source */ |
| 426 |
|
✗ |
RCC->CR |= (1 << RCC_CR_HSEON); |
| 427 |
|
|
} |
| 428 |
|
|
else{ |
| 429 |
|
|
/* do nothing */ |
| 430 |
|
|
} |
| 431 |
|
|
} |
| 432 |
|
|
|