GCC Code Coverage Report

Directory: src/drv/
File: src/drv/pwr/src/pwr_driver.c
Date: 2024-01-25 15:03:18
Exec Total Coverage
Lines: 0 92 0.0%
Branches: 0 33 0.0%
Line Branch Exec Source
1 /********************************************************************************************************//**
2 * @file pwr_driver.c
3 *
4 * @brief File containing the APIs for configuring the power peripheral.
5 *
6 * Public Functions:
7 * - void PWR_SetOverDrive(void)
8 * - void PWR_UnsetOverDrive(void)
9 * - void PWR_SetRegVoltageScal(PWR_RegVoltScal_t reg_volt_scal)
10 * - void PWR_DisableBackupWrProtec(void)
11 * - void PWR_EnableBackupWrProtec(void)
12 * - void PWR_EnterSTANDBY(void)
13 * - uint8_t PWR_EnableWakeupPin(PWR_WakeupPin_t pin)
14 * - uint8_t PWR_DisableWakeupPin(PWR_WakeupPin_t pin)
15 * - uint8_t PWR_CheckWakeupStandby(void)
16 * - void PWR_ClearWakeupFlag(void)
17 * - void PWR_ClearStandbyFlag(void)
18 * - void PWR_EnableBackupRegulator(void)
19 * - void PWR_DisableBackupRegulator(void)
20 * - void PWR_EnableFLASHPowerDown(uint8_t en_or_di)
21 * - void PWR_EnableUnderDrive(uint8_t en_or_di)
22 * - void PWR_EnableMRUnderDrive(uint8_t en_or_di)
23 * - void PWR_EnableLPRUnderDrive(uint8_t en_or_di)
24 * - void PWR_EnterStopMode(PWR_StopMode_t stop_mode, PWR_SleepMode_t sleep_mode)
25 *
26 * @note
27 * For further information about functions refer to the corresponding header file.
28 **/
29
30 #include "pwr_driver.h"
31 #include "cortex_m4.h"
32 #include "stm32f446xx.h"
33 #include <stdint.h>
34
35 /***********************************************************************************************************/
36 /* Public API Definitions */
37 /***********************************************************************************************************/
38
39 ✗ void PWR_SetOverDrive(void){
40
41 /* Set over-drive enable bit */
42 ✗ PWR->CR |= (1 << PWR_CR_ODEN);
43 /* Wait until over-drive mode ready */
44 ✗ while(!(PWR->CSR & (1 << PWR_CSR_ODRDY)));
45 /* Set over-driver switching bit */
46 ✗ PWR->CR |= (1 << PWR_CR_ODSWEN);
47 /* Wait until over drive mode is active */
48 ✗ while(!(PWR->CSR & (1 << PWR_CSR_ODSWRDY)));
49 }
50
51 ✗ void PWR_UnsetOverDrive(void){
52
53 ✗ uint32_t temp = 0;
54
55 /* Reset over-drive enable and over-drive switching bit */
56 ✗ temp |= ((1 << PWR_CR_ODEN) |
57 (1 << PWR_CR_ODSWEN));
58 ✗ PWR->CR &= ~temp;
59 /* Wait unitl over drive mode is inactive */
60 ✗ while(PWR->CSR & (1 << PWR_CSR_ODSWRDY));
61 }
62
63 ✗ void PWR_SetRegVoltageScal(PWR_RegVoltScal_t reg_volt_scal){
64
65 ✗ PWR->CR &= ~(0x2 << PWR_CR_VOS);
66 ✗ PWR->CR |= (reg_volt_scal << PWR_CR_VOS);
67 }
68
69 ✗ void PWR_DisableBackupWrProtec(void){
70
71 ✗ PWR->CR |= (1 << PWR_CR_DBP);
72 }
73
74 ✗ void PWR_EnableBackupWrProtec(void){
75
76 ✗ PWR->CR &= ~(1 << PWR_CR_DBP);
77 }
78
79 ✗ void PWR_EnterSTANDBY(void){
80
81 ✗ PWR->CR |= (1 << PWR_CR_PDDS);
82 ✗ EnableSleepDeep();
83 Enter_WFI();
84 }
85
86 ✗ uint8_t PWR_EnableWakeupPin(PWR_WakeupPin_t pin){
87
88 ✗ uint32_t temp = 0;
89
90 ✗ if(pin & 0xFFFFFE7F){
91 ✗ return 1;
92 }
93
94 ✗ temp |= pin;
95 ✗ PWR->CSR |= temp;
96
97 ✗ return 0;
98 }
99
100 ✗ uint8_t PWR_DisableWakeupPin(PWR_WakeupPin_t pin){
101
102 ✗ uint32_t temp = 0;
103
104 ✗ if(pin & 0xFFFFFE7F){
105 ✗ return 1;
106 }
107
108 ✗ temp |= pin;
109 ✗ PWR->CSR &= ~temp;
110
111 ✗ return 0;
112 }
113
114 ✗ uint8_t PWR_CheckWakeupStandby(void){
115
116 ✗ if(PWR->CSR & (1 << PWR_CSR_SBF)){
117 ✗ return 1;
118 }
119 else{
120 ✗ return 0;
121 }
122 }
123
124 ✗ void PWR_ClearWakeupFlag(void){
125
126 ✗ PWR->CR |= (1 << PWR_CR_CWUF);
127 }
128
129 ✗ void PWR_ClearStandbyFlag(void){
130
131 ✗ PWR->CR |= (1 << PWR_CR_CSBF);
132 }
133
134 ✗ void PWR_EnableBackupRegulator(void){
135
136 ✗ PWR->CSR |= (1 << PWR_CSR_BRE);
137 ✗ while(!(PWR->CSR & (1 << PWR_CSR_BRR)));
138 }
139
140 ✗ void PWR_DisableBackupRegulator(void){
141
142 ✗ PWR->CSR &= ~(1 << PWR_CSR_BRE);
143 ✗ while(PWR->CSR & (1 << PWR_CSR_BRR));
144 }
145
146 ✗ void PWR_EnableFLASHPowerDown(uint8_t en_or_di){
147
148 ✗ if(en_or_di == ENABLE){
149 ✗ PWR->CR |= (1 << PWR_CR_FPDS);
150 }
151 else{
152 ✗ PWR->CR &= ~(1 << PWR_CR_FPDS);
153 }
154 }
155
156 ✗ void PWR_EnableUnderDrive(uint8_t en_or_di){
157
158 ✗ if(en_or_di == ENABLE){
159 ✗ PWR->CR |= (0x3 << PWR_CR_UDEN);
160 }
161 else{
162 ✗ PWR->CR &= ~(0x3 << PWR_CR_UDEN);
163 }
164 }
165
166 ✗ void PWR_EnableMRUnderDrive(uint8_t en_or_di){
167
168 ✗ if(en_or_di == ENABLE){
169 ✗ PWR->CR |= (1 << PWR_CR_MRUDS);
170 }
171 else{
172 ✗ PWR->CR &= ~(1 << PWR_CR_MRUDS);
173 }
174 }
175
176 ✗ void PWR_EnableLPRUnderDrive(uint8_t en_or_di){
177
178 ✗ if(en_or_di == ENABLE){
179 ✗ PWR->CR |= (1 << PWR_CR_LPUDS);
180 }
181 else{
182 ✗ PWR->CR &= ~(1 << PWR_CR_LPUDS);
183 }
184 }
185
186 ✗ void PWR_EnterStopMode(PWR_StopMode_t stop_mode, PWR_SleepMode_t sleep_mode){
187
188 /* Clear all bits related with the stop mode configuration*/
189 ✗ PWR->CR &= ~0x000C0E01;
190
191 /* Configure bits in the PWR control register */
192 ✗ switch(stop_mode){
193 ✗ case PWR_STOP_MR:
194 /* MRUDS = 0, LPDS = 0, FPDS = 0 */
195 ✗ break;
196 ✗ case PWR_STOP_MR_FPD:
197 /* MRUDS = 0, LPDS = 0, FPDS = 1 */
198 ✗ PWR->CR |= (1 << PWR_CR_FPDS);
199 ✗ break;
200 ✗ case PWR_STOP_LP:
201 /* MRUDS = 0, LPUDS = 0, LPDS = 1, FPDS = 0 */
202 ✗ PWR->CR |= (1 << PWR_CR_LPDS);
203 ✗ break;
204 ✗ case PWR_STOP_LP_FPD:
205 /* MRUDS = 0, LPUDS = 0, LPDS = 1, FPDS = 1 */
206 ✗ PWR->CR |= (1 << PWR_CR_FPDS);
207 ✗ PWR->CR |= (1 << PWR_CR_LPDS);
208 ✗ break;
209 ✗ case PWR_STOP_UMR_FPD:
210 /* UDEN = 3, MRUDS = 1, LPDS = 0 */
211 ✗ PWR->CR |= (0x3 << PWR_CR_UDEN);
212 ✗ PWR->CR |= (1 << PWR_CR_MRUDS);
213 ✗ break;
214 ✗ case PWR_STOP_ULP_FPD:
215 /* UDEN = 3, LPUDS = 1, LPDS = 1 */
216 ✗ PWR->CR |= (0x3 << PWR_CR_UDEN);
217 ✗ PWR->CR |= (1 << PWR_CR_LPUDS);
218 ✗ PWR->CR |= (1 << PWR_CR_LPDS);
219 ✗ break;
220 ✗ default:
221 /* Do nothing */
222 ✗ break;
223 }
224
225 /* Enter in stop mode */
226 ✗ EnableSleepDeep();
227 ✗ if(sleep_mode == PWR_STOP_WFE){
228 Enter_WFE();
229 }
230 else{
231 Enter_WFI();
232 }
233 }
234