GCC Code Coverage Report

Directory: src/drv/
File: src/drv/dma/src/dma_driver.c
Date: 2024-01-25 15:03:18
Exec Total Coverage
Lines: 0 665 0.0%
Branches: 0 240 0.0%
Line Branch Exec Source
1 /********************************************************************************************************//**
2 * @file dma_driver.c
3 *
4 * @brief File containing the APIs for configuring the DMA peripheral.
5 *
6 * Public Functions:
7 * - void DMA_Init(DMA_Handle_t* pDMA_Handle)
8 * - void DMA_DeInit(DMA_RegDef_t* pDMAx)
9 * - void DMA_PerClkCtrl(DMA_RegDef_t* pDMAx, uint8_t en_or_di)
10 * - void DMA_Stream_Init(DMA_Stream_Handle_t* pDMA_Stream_Handle)
11 * - void DMA_Stream_Enable(DMA_Stream_Handle_t* pDMA_Stream_Handle){
12 * - void DMA_Stream_Set_NDTR(DMA_Stream_Handle_t* pDMA_Stream_Handle, uint32_t ndtr)
13 * - void DMA_Clear_Transfer_Compl_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
14 * - void DMA_Clear_Half_Transfer_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
15 * - void DMA_Clear_Transfer_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
16 * - void DMA_Clear_Direct_Mode_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
17 * - void DMA_Clear_FIFO_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
18 * - uint32_t DMA_Get_Transfer_Compl_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
19 * - uint32_t DMA_Get_Half_Transfer_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
20 * - uint32_t DMA_Get_Transfer_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
21 * - uint32_t DMA_Get_Direct_Mode_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
22 * - uint32_t DMA_Get_FIFO_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
23 * - void DMA_IRQHandling(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num)
24 * @note
25 * For further information about functions refer to the corresponding header file.
26 **/
27
28 #include "dma_driver.h"
29
30 /***********************************************************************************************************/
31 /* Static Function Prototypes */
32 /***********************************************************************************************************/
33
34 /**
35 * @brief Function to manage the transfer complete interrupt.
36 * @param[in] pDMAx the base address of the DMAx peripheral.
37 * @param[in] Stream_Num is the number of stream for clearing flag.
38 * @return void
39 */
40 static void Transfer_Complete_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num);
41
42 /**
43 * @brief Function to manage the half transfer interrupt.
44 * @param[in] pDMAx the base address of the DMAx peripheral.
45 * @param[in] Stream_Num is the number of stream for clearing flag.
46 * @return void
47 */
48 static void Half_Transfer_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num);
49
50 /**
51 * @brief Function to manage the transfer error interrupt.
52 * @param[in] pDMAx the base address of the DMAx peripheral.
53 * @param[in] Stream_Num is the number of stream for clearing flag.
54 * @return void
55 */
56 static void Transfer_Error_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num);
57
58 /**
59 * @brief Function to manage the direct mode error interrupt.
60 * @param[in] pDMAx the base address of the DMAx peripheral.
61 * @param[in] Stream_Num is the number of stream for clearing flag.
62 * @return void
63 */
64 static void Direct_Mode_Error_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num);
65
66 /**
67 * @brief Function to manage the FIFO error interrupt.
68 * @param[in] pDMAx the base address of the DMAx peripheral.
69 * @param[in] Stream_Num is the number of stream for clearing flag.
70 * @return void
71 */
72 static void FIFO_Error_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num);
73
74 /***********************************************************************************************************/
75 /* Public API Definitions */
76 /***********************************************************************************************************/
77
78 ✗ void DMA_Init(DMA_Handle_t* pDMA_Handle){
79
80 /* Enable the peripheral clock */
81 ✗ DMA_PerClkCtrl(pDMA_Handle->pDMAx, ENABLE);
82 }
83
84 ✗ void DMA_DeInit(DMA_RegDef_t* pDMAx){
85
86 ✗ if(pDMAx == DMA1){
87 ✗ DMA1_REG_RESET();
88 }
89 ✗ else if(pDMAx == DMA2){
90 ✗ DMA2_REG_RESET();
91 }
92 else{
93 /* do nothing */
94 }
95 }
96
97 ✗ void DMA_PerClkCtrl(DMA_RegDef_t* pDMAx, uint8_t en_or_di){
98
99 ✗ if(en_or_di == ENABLE){
100 ✗ if(pDMAx == DMA1){
101 ✗ DMA1_PCLK_EN();
102 }
103 ✗ else if(pDMAx == DMA2){
104 ✗ DMA2_PCLK_EN();
105 }
106 else{
107 /* do nothing */
108 }
109 }
110 else{
111 ✗ if(pDMAx == DMA1){
112 ✗ DMA1_PCLK_DI();
113 }
114 ✗ else if(pDMAx == DMA2){
115 ✗ DMA2_PCLK_DI();
116 }
117 else{
118 /* do nothing */
119 }
120 }
121 }
122
123 ✗ void DMA_Stream_Init(DMA_Stream_Handle_t* pDMA_Stream_Handle){
124
125 /* Set source address */
126 ✗ pDMA_Stream_Handle->pStreamx->M0AR = pDMA_Stream_Handle->Stream_Config.src_addr;
127
128 /* Set destination address */
129 ✗ pDMA_Stream_Handle->pStreamx->PAR = pDMA_Stream_Handle->Stream_Config.dst_addr;
130
131 /* Set number of data items to send */
132 ✗ pDMA_Stream_Handle->pStreamx->NDTR = (uint32_t)(pDMA_Stream_Handle->Stream_Config.num_data_register);
133
134 /* Set direction of the data transfer */
135 ✗ pDMA_Stream_Handle->pStreamx->CR &= ~(0x3 << DMA_SCR_DIR);
136 ✗ pDMA_Stream_Handle->pStreamx->CR |= (pDMA_Stream_Handle->Stream_Config.direction << DMA_SCR_DIR);
137
138 /* Set memory data size */
139 ✗ pDMA_Stream_Handle->pStreamx->CR &= ~(0x3 << DMA_SCR_MSIZE);
140 ✗ pDMA_Stream_Handle->pStreamx->CR |= (pDMA_Stream_Handle->Stream_Config.msize << DMA_SCR_MSIZE);
141
142 /* Set memory increment mode */
143 ✗ pDMA_Stream_Handle->pStreamx->CR &= ~(0x1 << DMA_SCR_MINC);
144 ✗ pDMA_Stream_Handle->pStreamx->CR |= (pDMA_Stream_Handle->Stream_Config.minc << DMA_SCR_MINC);
145
146 /* Set peripheral data size */
147 ✗ if(pDMA_Stream_Handle->Stream_Config.direction != M2M){
148 ✗ pDMA_Stream_Handle->pStreamx->CR &= ~(0x3 << DMA_SCR_PSIZE);
149 ✗ pDMA_Stream_Handle->pStreamx->CR |= (pDMA_Stream_Handle->Stream_Config.psize << DMA_SCR_PSIZE);
150 }
151
152 /* Set peripheral increment mode */
153 ✗ if(pDMA_Stream_Handle->Stream_Config.direction != M2M){
154 ✗ pDMA_Stream_Handle->pStreamx->CR &= ~(0x1 << DMA_SCR_PINC);
155 ✗ pDMA_Stream_Handle->pStreamx->CR |= (pDMA_Stream_Handle->Stream_Config.pinc << DMA_SCR_PINC);
156 }
157
158 /* Set circular mode */
159 ✗ pDMA_Stream_Handle->pStreamx->CR &= ~(0x1 << DMA_SCR_CIRC);
160 ✗ pDMA_Stream_Handle->pStreamx->CR |= (pDMA_Stream_Handle->Stream_Config.circular_mode << DMA_SCR_CIRC);
161
162 /* Set priority level */
163 ✗ pDMA_Stream_Handle->pStreamx->CR &= ~(0x3 << DMA_SCR_PL);
164 ✗ pDMA_Stream_Handle->pStreamx->CR |= (pDMA_Stream_Handle->Stream_Config.priority << DMA_SCR_PL);
165
166 /* Set channel number */
167 ✗ pDMA_Stream_Handle->pStreamx->CR &= ~(0x7 << DMA_SCR_CHSEL);
168 ✗ pDMA_Stream_Handle->pStreamx->CR |= (pDMA_Stream_Handle->Stream_Config.ch_number << DMA_SCR_CHSEL);
169
170 /* Set direct of FIFO mode */
171 ✗ pDMA_Stream_Handle->pStreamx->FCR &= ~(0x1 << DMA_SFCR_DMDIS);
172 ✗ pDMA_Stream_Handle->pStreamx->FCR |= (pDMA_Stream_Handle->Stream_Config.mode << DMA_SFCR_DMDIS);
173
174 /* Set FIFO threshold selection */
175 ✗ if(pDMA_Stream_Handle->Stream_Config.mode == FIFO_MODE){
176 ✗ pDMA_Stream_Handle->pStreamx->FCR &= ~(0x3 << DMA_SFCR_FTH);
177 ✗ pDMA_Stream_Handle->pStreamx->FCR |= (pDMA_Stream_Handle->Stream_Config.FIFO_thres << DMA_SFCR_FTH);
178 }
179
180 /* Set Half Transfer IE */
181 ✗ if(pDMA_Stream_Handle->Stream_Config.HTIE == ENABLE){
182 ✗ pDMA_Stream_Handle->pStreamx->CR |= (1 << DMA_SCR_HTIE);
183 }
184
185 /* Set Transfer Complete IE */
186 ✗ if(pDMA_Stream_Handle->Stream_Config.TCIE == ENABLE){
187 ✗ pDMA_Stream_Handle->pStreamx->CR |= (1 << DMA_SCR_TCIE);
188 }
189
190 /* Set Transfer Error IE */
191 ✗ if(pDMA_Stream_Handle->Stream_Config.TEIE == ENABLE){
192 ✗ pDMA_Stream_Handle->pStreamx->CR |= (1 << DMA_SCR_TEIE);
193 }
194
195 /* Set FIFO Error IE */
196 ✗ if(pDMA_Stream_Handle->Stream_Config.FEIE == ENABLE){
197 ✗ pDMA_Stream_Handle->pStreamx->FCR |= (1 << DMA_SFCR_FEIE);
198 }
199
200 /* Set Direct Mode Error IE */
201 ✗ if(pDMA_Stream_Handle->Stream_Config.DMEIE == ENABLE){
202 ✗ pDMA_Stream_Handle->pStreamx->CR |= (1 << DMA_SCR_DMEIE);
203 }
204 }
205
206 ✗ void DMA_Stream_Enable(DMA_Stream_Handle_t* pDMA_Stream_Handle){
207
208 /* Enable stream */
209 ✗ pDMA_Stream_Handle->pStreamx->CR |= (1 << DMA_SCR_EN);
210 }
211
212 ✗ void DMA_Stream_Set_NDTR(DMA_Stream_Handle_t* pDMA_Stream_Handle, uint32_t ndtr){
213
214 /* Set NDTR value */
215 ✗ pDMA_Stream_Handle->pStreamx->NDTR = ndtr;
216 }
217
218 ✗ void DMA_Clear_Transfer_Compl_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
219
220 ✗ switch(Stream_Num){
221 ✗ case STREAM0:
222 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CTCIF0);
223 ✗ break;
224 ✗ case STREAM1:
225 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CTCIF1);
226 ✗ break;
227 ✗ case STREAM2:
228 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CTCIF2);
229 ✗ break;
230 ✗ case STREAM3:
231 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CTCIF3);
232 ✗ break;
233 ✗ case STREAM4:
234 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CTCIF4);
235 ✗ break;
236 ✗ case STREAM5:
237 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CTCIF5);
238 ✗ break;
239 ✗ case STREAM6:
240 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CTCIF6);
241 ✗ break;
242 ✗ case STREAM7:
243 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CTCIF7);
244 ✗ break;
245 ✗ default:
246 ✗ break;
247 }
248 }
249
250 ✗ void DMA_Clear_Half_Transfer_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
251
252 ✗ switch(Stream_Num){
253 ✗ case STREAM0:
254 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CHTIF0);
255 ✗ break;
256 ✗ case STREAM1:
257 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CHTIF1);
258 ✗ break;
259 ✗ case STREAM2:
260 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CHTIF2);
261 ✗ break;
262 ✗ case STREAM3:
263 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CHTIF3);
264 ✗ break;
265 ✗ case STREAM4:
266 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CHTIF4);
267 ✗ break;
268 ✗ case STREAM5:
269 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CHTIF5);
270 ✗ break;
271 ✗ case STREAM6:
272 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CHTIF6);
273 ✗ break;
274 ✗ case STREAM7:
275 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CHTIF7);
276 ✗ break;
277 ✗ default:
278 ✗ break;
279 }
280 }
281
282 ✗ void DMA_Clear_Transfer_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
283
284 ✗ switch(Stream_Num){
285 ✗ case STREAM0:
286 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CTEIF0);
287 ✗ break;
288 ✗ case STREAM1:
289 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CTEIF1);
290 ✗ break;
291 ✗ case STREAM2:
292 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CTEIF2);
293 ✗ break;
294 ✗ case STREAM3:
295 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CTEIF3);
296 ✗ break;
297 ✗ case STREAM4:
298 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CTEIF4);
299 ✗ break;
300 ✗ case STREAM5:
301 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CTEIF5);
302 ✗ break;
303 ✗ case STREAM6:
304 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CTEIF6);
305 ✗ break;
306 ✗ case STREAM7:
307 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CTEIF7);
308 ✗ break;
309 ✗ default:
310 ✗ break;
311 }
312 }
313
314 ✗ void DMA_Clear_Direct_Mode_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
315
316 ✗ switch(Stream_Num){
317 ✗ case STREAM0:
318 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CDMEIF0);
319 ✗ break;
320 ✗ case STREAM1:
321 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CDMEIF1);
322 ✗ break;
323 ✗ case STREAM2:
324 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CDMEIF2);
325 ✗ break;
326 ✗ case STREAM3:
327 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CDMEIF3);
328 ✗ break;
329 ✗ case STREAM4:
330 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CDMEIF4);
331 ✗ break;
332 ✗ case STREAM5:
333 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CDMEIF5);
334 ✗ break;
335 ✗ case STREAM6:
336 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CDMEIF6);
337 ✗ break;
338 ✗ case STREAM7:
339 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CDMEIF7);
340 ✗ break;
341 ✗ default:
342 ✗ break;
343 }
344 }
345
346 ✗ void DMA_Clear_FIFO_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
347
348 ✗ switch(Stream_Num){
349 ✗ case STREAM0:
350 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CFEIF0);
351 ✗ break;
352 ✗ case STREAM1:
353 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CFEIF1);
354 ✗ break;
355 ✗ case STREAM2:
356 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CFEIF2);
357 ✗ break;
358 ✗ case STREAM3:
359 ✗ pDMAx->LIFCR |= (1 << DMA_LIFCR_CFEIF3);
360 ✗ break;
361 ✗ case STREAM4:
362 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CFEIF4);
363 ✗ break;
364 ✗ case STREAM5:
365 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CFEIF5);
366 ✗ break;
367 ✗ case STREAM6:
368 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CFEIF6);
369 ✗ break;
370 ✗ case STREAM7:
371 ✗ pDMAx->HIFCR |= (1 << DMA_HIFCR_CFEIF7);
372 ✗ break;
373 ✗ default:
374 ✗ break;
375 }
376 }
377
378 ✗ uint32_t DMA_Get_Transfer_Compl_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
379
380 ✗ uint32_t ret = 0;
381
382 ✗ switch(Stream_Num){
383 ✗ case STREAM0:
384 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_TCIF0);
385 ✗ break;
386 ✗ case STREAM1:
387 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_TCIF1);
388 ✗ break;
389 ✗ case STREAM2:
390 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_TCIF2);
391 ✗ break;
392 ✗ case STREAM3:
393 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_TCIF3);
394 ✗ break;
395 ✗ case STREAM4:
396 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_TCIF4);
397 ✗ break;
398 ✗ case STREAM5:
399 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_TCIF5);
400 ✗ break;
401 ✗ case STREAM6:
402 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_TCIF6);
403 ✗ break;
404 ✗ case STREAM7:
405 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_TCIF7);
406 ✗ break;
407 ✗ default:
408 ✗ break;
409 }
410
411 ✗ return ret;
412 }
413
414 ✗ uint32_t DMA_Get_Half_Transfer_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
415
416 ✗ uint32_t ret = 0;
417
418 ✗ switch(Stream_Num){
419 ✗ case STREAM0:
420 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_HTIF0);
421 ✗ break;
422 ✗ case STREAM1:
423 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_HTIF1);
424 ✗ break;
425 ✗ case STREAM2:
426 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_HTIF2);
427 ✗ break;
428 ✗ case STREAM3:
429 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_HTIF3);
430 ✗ break;
431 ✗ case STREAM4:
432 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_HTIF4);
433 ✗ break;
434 ✗ case STREAM5:
435 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_HTIF5);
436 ✗ break;
437 ✗ case STREAM6:
438 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_HTIF6);
439 ✗ break;
440 ✗ case STREAM7:
441 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_HTIF7);
442 ✗ break;
443 ✗ default:
444 ✗ break;
445 }
446
447 ✗ return ret;
448 }
449
450 ✗ uint32_t DMA_Get_Transfer_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
451
452 ✗ uint32_t ret = 0;
453
454 ✗ switch(Stream_Num){
455 ✗ case STREAM0:
456 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_TEIF0);
457 ✗ break;
458 ✗ case STREAM1:
459 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_TEIF1);
460 ✗ break;
461 ✗ case STREAM2:
462 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_TEIF2);
463 ✗ break;
464 ✗ case STREAM3:
465 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_TEIF3);
466 ✗ break;
467 ✗ case STREAM4:
468 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_TEIF4);
469 ✗ break;
470 ✗ case STREAM5:
471 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_TEIF5);
472 ✗ break;
473 ✗ case STREAM6:
474 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_TEIF6);
475 ✗ break;
476 ✗ case STREAM7:
477 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_TEIF7);
478 ✗ break;
479 ✗ default:
480 ✗ break;
481 }
482
483 ✗ return ret;
484 }
485
486 ✗ uint32_t DMA_Get_Direct_Mode_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
487
488 ✗ uint32_t ret = 0;
489
490 ✗ switch(Stream_Num){
491 ✗ case STREAM0:
492 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_DMEIF0);
493 ✗ break;
494 ✗ case STREAM1:
495 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_DMEIF1);
496 ✗ break;
497 ✗ case STREAM2:
498 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_DMEIF2);
499 ✗ break;
500 ✗ case STREAM3:
501 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_DMEIF3);
502 ✗ break;
503 ✗ case STREAM4:
504 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_DMEIF4);
505 ✗ break;
506 ✗ case STREAM5:
507 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_DMEIF5);
508 ✗ break;
509 ✗ case STREAM6:
510 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_DMEIF6);
511 ✗ break;
512 ✗ case STREAM7:
513 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_DMEIF7);
514 ✗ break;
515 ✗ default:
516 ✗ break;
517 }
518
519 ✗ return ret;
520 }
521
522 ✗ uint32_t DMA_Get_FIFO_Error_Int_Flag(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
523
524 ✗ uint32_t ret = 0;
525
526 ✗ switch(Stream_Num){
527 ✗ case STREAM0:
528 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_FEIF0);
529 ✗ break;
530 ✗ case STREAM1:
531 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_FEIF1);
532 ✗ break;
533 ✗ case STREAM2:
534 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_FEIF2);
535 ✗ break;
536 ✗ case STREAM3:
537 ✗ ret = pDMAx->LISR & (1 << DMA_LISR_FEIF3);
538 ✗ break;
539 ✗ case STREAM4:
540 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_FEIF4);
541 ✗ break;
542 ✗ case STREAM5:
543 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_FEIF5);
544 ✗ break;
545 ✗ case STREAM6:
546 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_FEIF6);
547 ✗ break;
548 ✗ case STREAM7:
549 ✗ ret = pDMAx->HISR & (1 << DMA_HISR_FEIF7);
550 ✗ break;
551 ✗ default:
552 ✗ break;
553 }
554
555 ✗ return ret;
556 }
557
558 ✗ void DMA_IRQHandling(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
559
560 ✗ if(DMA_Get_Transfer_Compl_Int_Flag(pDMAx, Stream_Num)){
561 ✗ DMA_Clear_Transfer_Compl_Int_Flag(pDMAx, Stream_Num);
562 ✗ Transfer_Complete_Callback(pDMAx, Stream_Num);
563 }
564 ✗ else if(DMA_Get_Half_Transfer_Int_Flag(pDMAx, Stream_Num)){
565 ✗ DMA_Clear_Half_Transfer_Int_Flag(pDMAx, Stream_Num);
566 ✗ Half_Transfer_Callback(pDMAx, Stream_Num);
567 }
568 ✗ else if(DMA_Get_Transfer_Error_Int_Flag(pDMAx, Stream_Num)){
569 ✗ DMA_Clear_Transfer_Error_Int_Flag(pDMAx, Stream_Num);
570 ✗ Transfer_Error_Callback(pDMAx, Stream_Num);
571 }
572 ✗ else if(DMA_Get_Direct_Mode_Error_Int_Flag(pDMAx, Stream_Num)){
573 ✗ DMA_Clear_Direct_Mode_Error_Int_Flag(pDMAx, Stream_Num);
574 ✗ Direct_Mode_Error_Callback(pDMAx, Stream_Num);
575 }
576 ✗ else if(DMA_Get_FIFO_Error_Int_Flag(pDMAx, Stream_Num)){
577 ✗ DMA_Clear_FIFO_Error_Int_Flag(pDMAx, Stream_Num);
578 ✗ FIFO_Error_Callback(pDMAx, Stream_Num);
579 }
580 else{
581 }
582 }
583
584 /***********************************************************************************************************/
585 /* Weak Functions */
586 /* This is a weak implementation. The application may override this function */
587 /***********************************************************************************************************/
588
589 ✗ __attribute__((weak)) void DMA1_Stream0_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
590 ✗ __attribute__((weak)) void DMA1_Stream1_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
591 ✗ __attribute__((weak)) void DMA1_Stream2_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
592 ✗ __attribute__((weak)) void DMA1_Stream3_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
593 ✗ __attribute__((weak)) void DMA1_Stream4_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
594 ✗ __attribute__((weak)) void DMA1_Stream5_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
595 ✗ __attribute__((weak)) void DMA1_Stream6_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
596 ✗ __attribute__((weak)) void DMA1_Stream7_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
597 ✗ __attribute__((weak)) void DMA2_Stream0_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
598 ✗ __attribute__((weak)) void DMA2_Stream1_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
599 ✗ __attribute__((weak)) void DMA2_Stream2_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
600 ✗ __attribute__((weak)) void DMA2_Stream3_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
601 ✗ __attribute__((weak)) void DMA2_Stream4_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
602 ✗ __attribute__((weak)) void DMA2_Stream5_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
603 ✗ __attribute__((weak)) void DMA2_Stream6_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
604 ✗ __attribute__((weak)) void DMA2_Stream7_AppEventCallback(DMA_App_Event_t app_event){ (void)app_event; }
605
606 /***********************************************************************************************************/
607 /* Static Function Definitions */
608 /***********************************************************************************************************/
609
610 ✗ void Transfer_Complete_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
611
612 ✗ if(pDMAx == DMA1){
613 ✗ switch(Stream_Num){
614 ✗ case STREAM0:
615 ✗ DMA1_Stream0_AppEventCallback(TRANSFER_COMPLETE);
616 ✗ break;
617 ✗ case STREAM1:
618 ✗ DMA1_Stream1_AppEventCallback(TRANSFER_COMPLETE);
619 ✗ break;
620 ✗ case STREAM2:
621 ✗ DMA1_Stream2_AppEventCallback(TRANSFER_COMPLETE);
622 ✗ break;
623 ✗ case STREAM3:
624 ✗ DMA1_Stream3_AppEventCallback(TRANSFER_COMPLETE);
625 ✗ break;
626 ✗ case STREAM4:
627 ✗ DMA1_Stream4_AppEventCallback(TRANSFER_COMPLETE);
628 ✗ break;
629 ✗ case STREAM5:
630 ✗ DMA1_Stream5_AppEventCallback(TRANSFER_COMPLETE);
631 ✗ break;
632 ✗ case STREAM6:
633 ✗ DMA1_Stream6_AppEventCallback(TRANSFER_COMPLETE);
634 ✗ break;
635 ✗ case STREAM7:
636 ✗ DMA1_Stream7_AppEventCallback(TRANSFER_COMPLETE);
637 ✗ break;
638 ✗ default:
639 ✗ break;
640 }
641 }
642 ✗ else if(pDMAx == DMA2){
643 ✗ switch(Stream_Num){
644 ✗ case STREAM0:
645 ✗ DMA2_Stream0_AppEventCallback(TRANSFER_COMPLETE);
646 ✗ break;
647 ✗ case STREAM1:
648 ✗ DMA2_Stream1_AppEventCallback(TRANSFER_COMPLETE);
649 ✗ break;
650 ✗ case STREAM2:
651 ✗ DMA2_Stream2_AppEventCallback(TRANSFER_COMPLETE);
652 ✗ break;
653 ✗ case STREAM3:
654 ✗ DMA2_Stream3_AppEventCallback(TRANSFER_COMPLETE);
655 ✗ break;
656 ✗ case STREAM4:
657 ✗ DMA2_Stream4_AppEventCallback(TRANSFER_COMPLETE);
658 ✗ break;
659 ✗ case STREAM5:
660 ✗ DMA2_Stream5_AppEventCallback(TRANSFER_COMPLETE);
661 ✗ break;
662 ✗ case STREAM6:
663 ✗ DMA2_Stream6_AppEventCallback(TRANSFER_COMPLETE);
664 ✗ break;
665 ✗ case STREAM7:
666 ✗ DMA2_Stream7_AppEventCallback(TRANSFER_COMPLETE);
667 ✗ break;
668 ✗ default:
669 ✗ break;
670 }
671 }
672 else{
673 /* do nothing */
674 }
675 }
676
677 ✗ void Half_Transfer_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
678
679 ✗ if(pDMAx == DMA1){
680 ✗ switch(Stream_Num){
681 ✗ case STREAM0:
682 ✗ DMA1_Stream0_AppEventCallback(HALF_TRANSFER);
683 ✗ break;
684 ✗ case STREAM1:
685 ✗ DMA1_Stream1_AppEventCallback(HALF_TRANSFER);
686 ✗ break;
687 ✗ case STREAM2:
688 ✗ DMA1_Stream2_AppEventCallback(HALF_TRANSFER);
689 ✗ break;
690 ✗ case STREAM3:
691 ✗ DMA1_Stream3_AppEventCallback(HALF_TRANSFER);
692 ✗ break;
693 ✗ case STREAM4:
694 ✗ DMA1_Stream4_AppEventCallback(HALF_TRANSFER);
695 ✗ break;
696 ✗ case STREAM5:
697 ✗ DMA1_Stream5_AppEventCallback(HALF_TRANSFER);
698 ✗ break;
699 ✗ case STREAM6:
700 ✗ DMA1_Stream6_AppEventCallback(HALF_TRANSFER);
701 ✗ break;
702 ✗ case STREAM7:
703 ✗ DMA1_Stream7_AppEventCallback(HALF_TRANSFER);
704 ✗ break;
705 ✗ default:
706 ✗ break;
707 }
708 }
709 ✗ else if(pDMAx == DMA2){
710 ✗ switch(Stream_Num){
711 ✗ case STREAM0:
712 ✗ DMA2_Stream0_AppEventCallback(HALF_TRANSFER);
713 ✗ break;
714 ✗ case STREAM1:
715 ✗ DMA2_Stream1_AppEventCallback(HALF_TRANSFER);
716 ✗ break;
717 ✗ case STREAM2:
718 ✗ DMA2_Stream2_AppEventCallback(HALF_TRANSFER);
719 ✗ break;
720 ✗ case STREAM3:
721 ✗ DMA2_Stream3_AppEventCallback(HALF_TRANSFER);
722 ✗ break;
723 ✗ case STREAM4:
724 ✗ DMA2_Stream4_AppEventCallback(HALF_TRANSFER);
725 ✗ break;
726 ✗ case STREAM5:
727 ✗ DMA2_Stream5_AppEventCallback(HALF_TRANSFER);
728 ✗ break;
729 ✗ case STREAM6:
730 ✗ DMA2_Stream6_AppEventCallback(HALF_TRANSFER);
731 ✗ break;
732 ✗ case STREAM7:
733 ✗ DMA2_Stream7_AppEventCallback(HALF_TRANSFER);
734 ✗ break;
735 ✗ default:
736 ✗ break;
737 }
738 }
739 else{
740 /* do nothing */
741 }
742 }
743
744 ✗ void Transfer_Error_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
745
746 ✗ if(pDMAx == DMA1){
747 ✗ switch(Stream_Num){
748 ✗ case STREAM0:
749 ✗ DMA1_Stream0_AppEventCallback(TRANSFER_ERROR);
750 ✗ break;
751 ✗ case STREAM1:
752 ✗ DMA1_Stream1_AppEventCallback(TRANSFER_ERROR);
753 ✗ break;
754 ✗ case STREAM2:
755 ✗ DMA1_Stream2_AppEventCallback(TRANSFER_ERROR);
756 ✗ break;
757 ✗ case STREAM3:
758 ✗ DMA1_Stream3_AppEventCallback(TRANSFER_ERROR);
759 ✗ break;
760 ✗ case STREAM4:
761 ✗ DMA1_Stream4_AppEventCallback(TRANSFER_ERROR);
762 ✗ break;
763 ✗ case STREAM5:
764 ✗ DMA1_Stream5_AppEventCallback(TRANSFER_ERROR);
765 ✗ break;
766 ✗ case STREAM6:
767 ✗ DMA1_Stream6_AppEventCallback(TRANSFER_ERROR);
768 ✗ break;
769 ✗ case STREAM7:
770 ✗ DMA1_Stream7_AppEventCallback(TRANSFER_ERROR);
771 ✗ break;
772 ✗ default:
773 ✗ break;
774 }
775 }
776 ✗ else if(pDMAx == DMA2){
777 ✗ switch(Stream_Num){
778 ✗ case STREAM0:
779 ✗ DMA2_Stream0_AppEventCallback(TRANSFER_ERROR);
780 ✗ break;
781 ✗ case STREAM1:
782 ✗ DMA2_Stream1_AppEventCallback(TRANSFER_ERROR);
783 ✗ break;
784 ✗ case STREAM2:
785 ✗ DMA2_Stream2_AppEventCallback(TRANSFER_ERROR);
786 ✗ break;
787 ✗ case STREAM3:
788 ✗ DMA2_Stream3_AppEventCallback(TRANSFER_ERROR);
789 ✗ break;
790 ✗ case STREAM4:
791 ✗ DMA2_Stream4_AppEventCallback(TRANSFER_ERROR);
792 ✗ break;
793 ✗ case STREAM5:
794 ✗ DMA2_Stream5_AppEventCallback(TRANSFER_ERROR);
795 ✗ break;
796 ✗ case STREAM6:
797 ✗ DMA2_Stream6_AppEventCallback(TRANSFER_ERROR);
798 ✗ break;
799 ✗ case STREAM7:
800 ✗ DMA2_Stream7_AppEventCallback(TRANSFER_ERROR);
801 ✗ break;
802 ✗ default:
803 ✗ break;
804 }
805 }
806 else{
807 /* do nothing */
808 }
809 }
810
811 ✗ void Direct_Mode_Error_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
812
813 ✗ if(pDMAx == DMA1){
814 ✗ switch(Stream_Num){
815 ✗ case STREAM0:
816 ✗ DMA1_Stream0_AppEventCallback(DIRECT_MODE_ERROR);
817 ✗ break;
818 ✗ case STREAM1:
819 ✗ DMA1_Stream1_AppEventCallback(DIRECT_MODE_ERROR);
820 ✗ break;
821 ✗ case STREAM2:
822 ✗ DMA1_Stream2_AppEventCallback(DIRECT_MODE_ERROR);
823 ✗ break;
824 ✗ case STREAM3:
825 ✗ DMA1_Stream3_AppEventCallback(DIRECT_MODE_ERROR);
826 ✗ break;
827 ✗ case STREAM4:
828 ✗ DMA1_Stream4_AppEventCallback(DIRECT_MODE_ERROR);
829 ✗ break;
830 ✗ case STREAM5:
831 ✗ DMA1_Stream5_AppEventCallback(DIRECT_MODE_ERROR);
832 ✗ break;
833 ✗ case STREAM6:
834 ✗ DMA1_Stream6_AppEventCallback(DIRECT_MODE_ERROR);
835 ✗ break;
836 ✗ case STREAM7:
837 ✗ DMA1_Stream7_AppEventCallback(DIRECT_MODE_ERROR);
838 ✗ break;
839 ✗ default:
840 ✗ break;
841 }
842 }
843 ✗ else if(pDMAx == DMA2){
844 ✗ switch(Stream_Num){
845 ✗ case STREAM0:
846 ✗ DMA2_Stream0_AppEventCallback(DIRECT_MODE_ERROR);
847 ✗ break;
848 ✗ case STREAM1:
849 ✗ DMA2_Stream1_AppEventCallback(DIRECT_MODE_ERROR);
850 ✗ break;
851 ✗ case STREAM2:
852 ✗ DMA2_Stream2_AppEventCallback(DIRECT_MODE_ERROR);
853 ✗ break;
854 ✗ case STREAM3:
855 ✗ DMA2_Stream3_AppEventCallback(DIRECT_MODE_ERROR);
856 ✗ break;
857 ✗ case STREAM4:
858 ✗ DMA2_Stream4_AppEventCallback(DIRECT_MODE_ERROR);
859 ✗ break;
860 ✗ case STREAM5:
861 ✗ DMA2_Stream5_AppEventCallback(DIRECT_MODE_ERROR);
862 ✗ break;
863 ✗ case STREAM6:
864 ✗ DMA2_Stream6_AppEventCallback(DIRECT_MODE_ERROR);
865 ✗ break;
866 ✗ case STREAM7:
867 ✗ DMA2_Stream7_AppEventCallback(DIRECT_MODE_ERROR);
868 ✗ break;
869 ✗ default:
870 ✗ break;
871 }
872 }
873 else{
874 /* do nothing */
875 }
876 }
877
878 ✗ void FIFO_Error_Callback(DMA_RegDef_t* pDMAx, DMA_Stream_Num_t Stream_Num){
879
880 ✗ if(pDMAx == DMA1){
881 ✗ switch(Stream_Num){
882 ✗ case STREAM0:
883 ✗ DMA1_Stream0_AppEventCallback(FIFO_ERROR);
884 ✗ break;
885 ✗ case STREAM1:
886 ✗ DMA1_Stream1_AppEventCallback(FIFO_ERROR);
887 ✗ break;
888 ✗ case STREAM2:
889 ✗ DMA1_Stream2_AppEventCallback(FIFO_ERROR);
890 ✗ break;
891 ✗ case STREAM3:
892 ✗ DMA1_Stream3_AppEventCallback(FIFO_ERROR);
893 ✗ break;
894 ✗ case STREAM4:
895 ✗ DMA1_Stream4_AppEventCallback(FIFO_ERROR);
896 ✗ break;
897 ✗ case STREAM5:
898 ✗ DMA1_Stream5_AppEventCallback(FIFO_ERROR);
899 ✗ break;
900 ✗ case STREAM6:
901 ✗ DMA1_Stream6_AppEventCallback(FIFO_ERROR);
902 ✗ break;
903 ✗ case STREAM7:
904 ✗ DMA1_Stream7_AppEventCallback(FIFO_ERROR);
905 ✗ break;
906 ✗ default:
907 ✗ break;
908 }
909 }
910 ✗ else if(pDMAx == DMA2){
911 ✗ switch(Stream_Num){
912 ✗ case STREAM0:
913 ✗ DMA2_Stream0_AppEventCallback(FIFO_ERROR);
914 ✗ break;
915 ✗ case STREAM1:
916 ✗ DMA2_Stream1_AppEventCallback(FIFO_ERROR);
917 ✗ break;
918 ✗ case STREAM2:
919 ✗ DMA2_Stream2_AppEventCallback(FIFO_ERROR);
920 ✗ break;
921 ✗ case STREAM3:
922 ✗ DMA2_Stream3_AppEventCallback(FIFO_ERROR);
923 ✗ break;
924 ✗ case STREAM4:
925 ✗ DMA2_Stream4_AppEventCallback(FIFO_ERROR);
926 ✗ break;
927 ✗ case STREAM5:
928 ✗ DMA2_Stream5_AppEventCallback(FIFO_ERROR);
929 ✗ break;
930 ✗ case STREAM6:
931 ✗ DMA2_Stream6_AppEventCallback(FIFO_ERROR);
932 ✗ break;
933 ✗ case STREAM7:
934 ✗ DMA2_Stream7_AppEventCallback(FIFO_ERROR);
935 ✗ break;
936 ✗ default:
937 ✗ break;
938 }
939 }
940 else{
941 /* do nothing */
942 }
943 }
944